VLSI RTL Design Engineer Jobs in Chennai Embedded Systems and Firmware Company

📋 Job Description

Jobzi is sourcing qualified candidates for VLSI RTL Design Engineer positions in Chennai's private Embedded Systems and Firmware Company sector. This is a full-time opportunity with a reputed Embedded Systems and VLSI employer in Chennai offering competitive salary, structured growth, and a professional work environment. Tamil communication skills are preferred alongside English for professional and business interaction in Chennai.

📌 Key Responsibilities

• Write synthesisable RTL in SystemVerilog or Verilog for digital ICs and SoC sub-blocks
• Develop micro-architecture specifications and translate them into RTL implementations
• Run synthesis using Synopsys Design Compiler or Cadence Genus and meet timing targets
• Perform CDC analysis and apply proper synchronisation structures
• Run Spyglass or similar lint tools to ensure RTL quality and coding standard compliance
• Apply UPF power intent for multi-voltage and clock gating low-power design techniques
• Collaborate with verification engineers to resolve RTL bugs found in simulation and emulation

🎓 Qualifications and Requirements

• Explain the difference between blocking and non-blocking assignments and when each is correct.
• How do you write a parameterised FIFO in SystemVerilog that is safe for synthesis?
• What is glitch power and how do you reduce it using clock gating in RTL?
• How do you structure a synchroniser for a 2-flop metastability protection for CDC?
• Describe your experience running Synopsys Design Compiler for a 20k gate design.
• What Spyglass rule categories do you prioritise when starting a lint run on new RTL?
• How do you write a UPF file to describe always-on and power-switched domains?
• Good Tamil and English communication skills for team coordination and client interaction in Chennai.

✅ Required Skills